The present invention relates to integrated circuits, and more particularly to dielectric formed in trenches in a silicon substrate. Some embodiments are suitable for substrate isolation for integrated circuits.
FIG. 1 illustrates an intermediate structure in a flash memory fabrication process using shallow trench isolation (ST1). Silicon dioxide 110 (“pad oxide”) is thermally grown on silicon substrate 120. Silicon nitride 130 is formed on oxide 110 and patterned photolithographically to define substrate isolation trenches 134 to be formed between active areas 140. Oxide 110 and substrate 140 are etched through the openings in nitride 130 to form the isolation trenches. Silicon dioxide 150 is deposited to fill the trenches and cover the wafer. Oxide 150 is polished by chemical mechanical polishing (CMP) until the top surface of nitride 130 is exposed. A planar top wafer surface is provided.
Oxide 150 can be etched down (FIG. 2) to achieve a more planar topography in subsequent steps. Nitride 130 and pad oxide 110 are etched away (FIG. 3). Silicon dioxide 410 (“tunnel oxide”) is thermally grown to a desired thickness (e.g. 9 nm). A doped polysilicon layer 510 (FIG. 5) is deposited on oxide layers 410, 150 to provide the floating gates and is partially patterned. Dielectric 520 (e.g. a sandwich of silicon dioxide, silicon nitride, silicon dioxide, i.e. ONO) is formed over the structure. Doped polysilicon 530 is deposited on ONO 520. Layers 530, 520, 510 are patterned together to create wordlines form the layer 530 and to finish the patterning of the floating gate. Source/drain regions 610 (top view in FIG. 6) are formed on each side of each floating gate. The cross sectional plane of FIG. 5 is marked V-V in FIG. 6. Floating gates 510 are shown with crosses in FIG. 6. Additional layers (not shown) are deposited and patterned to provide conductive bitlines contacting some of the source/drain regions. See e.g. U.S. Pat. No. 6,265,292 issued Jul. 24, 2001 to Parat et al. and incorporated herein by reference.
The electric field is undesirably increased at sharp corners 140C (FIGS. 4, 5) during the circuit operation. In addition, the growth of tunnel oxide 410 (FIG. 4) is retarded at these corners, so oxide 410 is thinner at the corners than in the middle of the active areas. The oxide thinning further increases the electric field at the corners, creating overerase and/or other problems (depending on the memory operation). See U.S. patent application published as no. US 2004/0014269 on Jan. 22, 2004, incorporated herein by reference. It is desirable to round the trench corners 410C to provide a uniform thickness oxide 410 and reduce the electric field at the corners, as illustrated in FIG. 7 (showing the wafer with rounded corners 410C at the stage of FIG. 1) and in FIG. 8 (the wafer with rounded corners at the stage of FIG. 3).
To round the corners 140C, oxide 150 can be formed by first growing a thin silicon dioxide liner on the trench surface by thermal oxidation. The oxidation rounds the corners 140C. Then the rest of oxide 150 can be deposited (by a high density plasma process, i.e. HDP, or some other technique). The rounding should be controlled to minimize the active area consumption. If the corners are at the [111] crystallographic plane and the trench sidewalls are at [100], a chlorine source can be used in the liner formation to provide a desired rounding without an undue consumption of the active area. See PCT application published as WO 01/47010 on 28 Jun. 2001 and incorporated herein by reference.
Improved corner rounding techniques for flash memories and other integrated circuits are desirable.